《計(jì)算機(jī)組織與結(jié)構(gòu)：性能設(shè)計(jì)（第8版）（英文版）》以Intel x86系列通用處理器和ARM系列嵌入式處理器作為主要考察實(shí)例，將當(dāng)代計(jì)算機(jī)系統(tǒng)性能設(shè)計(jì)問題和計(jì)算機(jī)組織與結(jié)構(gòu)的基本概念及原理緊密聯(lián)系。首先介紹計(jì)算機(jī)的發(fā)展與演變，引入性能評價(jià)和性能設(shè)計(jì)的概念，然后以自頂而下的方式逐層展開介紹計(jì)算機(jī)系統(tǒng)、存儲(chǔ)器體系結(jié)構(gòu)、I/O及互連、計(jì)算機(jī)算術(shù)、指令集體系結(jié)構(gòu)的設(shè)計(jì)及其實(shí)現(xiàn)技術(shù)、控制器設(shè)計(jì)，最后還介紹了處理器的各種并行組織技術(shù)。本書特色在于探討和揭示面向性能的各種設(shè)計(jì)博弈和實(shí)現(xiàn)考量，追逐性能極大化的同時(shí)顧及系統(tǒng)整體的性能平衡。
Chapter 1 Reader’s Guide
0.1 Outline of the Book
0.2 A Roadmap for Readers and Instructors
0.3 Why Study Computer Organization and Architecture
0.4 Internet and Web Resources
PART ONE OVERVIEW
Chapter 2 Introduction
1.1 Organization and Architecture
1.2 Structure and Function
1.3 Key Terms and Review Questions
Chapter Computer Evolution and Performance
2.1 A Brief History of Computers
2.2 Designing for Performance
2.3 The Evolution of the Intel x86 Architecture
2.4 Embedded Systems and the ARM
2.5 Performance Assessment
2.6 Recommended Reading and Web Sites
2.7 Key Terms, Review Questions, and Problems
PART TWO THE COMPUTER SYSTEM
Chapter 3 A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 PCI
3.6 Recommended Reading and Web Sites
3.7 Key Terms, Review Questions, and Problems
Appendix A Timing Diagrams
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium Cache Organization
4.5 ARM Cache Organization
4.6 Recommended Reading
4.7 Key Terms, Review Questions, and Problems
Appendix A Performance Characteristics of Two-Level Memories
Chapter 5 Internal Memory Technology
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced DRAM Organization
5.4 Recommended Reading and Web Sites
5.5 Key Terms, Review Questions, and Problems
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Optical Memory
6.4 Magnetic Tape
6.5 Recommended Reading and Web Sites
6.6 Key Terms, Review Questions, and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules 2
7.3 Programmed I/O
7.4 Interrupt-Driven I/O 8
7.5 Direct Memory Access
7.6 I/O Channels and Processors
7.7 The External Interface: FireWire and Infiniband
7.8 Recommended Reading and Web Sites
7.9 Key Terms, Review Questions, and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Pentium Memory Management
8.5 ARM Memory Management
8.6 Recommended Reading and Web Sites
8.7 Key Terms, Review Questions, and Problems
PART THREE THE CENTRAL PROCESSING UNIT
Chapter 9 Computer Arithmetic
9.1 The Arithmetic and Logic Unit (ALU)
9.2 Integer Representation
9.3 Integer Arithmetic
9.4 Floating-Point Representation
9.5 Floating-Point Arithmetic
9.6 Recommended Reading and Web Sites
9.7 Key Terms, Review Questions, and Problems
Chapter 10 Instruction Sets: Characteristics and Functions
10.1 Machine Instruction Characteristics
10.2 Types of Operands
10.3 Intel x86 and ARM Data Types
10.4 Types of Operations
10.5 Intel x86 and ARM Operation Types
10.6 Recommended Reading
10.7 Key Terms, Review Questions, and Problems
Appendix A Stacks
Appendix B Little, Big, and Bi-Endian
Chapter 11 Instruction Sets: Addressing Modes and Formats
11.1 Addressing
11.2 x86 and ARM Addressing Modes
11.3 Instruction Formats
11.4 x86 and ARM Instruction Formats
11.5 Assembly Language
11.6 Recommended Reading
11.7 Key Terms, Review Questions, and Problems
Chapter 12 Processor Structure and Function
12.1 Processor Organization
12.2 Register Organization
12.3 The Instruction Cycle
12.4 Instruction Pipelining
12.5 The x86 Processor Family
12.6 The ARM Processor
12.7 Recommended Reading
12.8 Key Terms, Review Questions, and Problems
Chapter 13 Reduced Instruction Set Computers (RISCs)
13.1 Instruction Execution Characteristics
13.2 The Use of a Large Register File
13.3 Compiler-Based Register Optimization
13.4 Reduced Instruction Set Architecture
13.5 RISC Pipelining
13.6 MIPS R4000
13.7 SPARC
13.8 The RISC versus CISC Controversy
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