本書采用ARM取代了早先使用MIPS作為核心處理器來介紹計算機組織和設計的基本概念，涵蓋了數字邏輯設計的主要內容。本書以一種流行的方式介紹了從計算機組織和設計到更細節層次的內容，涵蓋了數字邏輯設計的主要內容，并通過ARM微處理器的設計強化數字邏輯的概念。本書的典型特色是將數字邏輯和計算機體系結構融合，教學內容反映了當前數字電路設計的主流方法，并突出計算機體系結構的工程特點，書中的大量示例及習題也可以加強讀者對基本概念和技術的理解和記憶。
PrefaceThis book is unique in its treatment in that it presents digital logic design from the perspective of computer architecture,starting at the beginning with 1’s and 0’s,and leading through the design of a microprocessor.We believe that building a microprocessor is a special rite of passage for engineering and computer science students.The inner workings of a proces-sor seem almost magical to the uninitiated,yet prove to be straightforward when carefully explained.Digital design in itself is a powerful and exciting subject.Assembly language programming unveils the inner language spoken by the processor.Microarchitecture is the link that brings it all together.The first two editions of this increasingly popular text have covered the MIPS architecture in the tradition of the widely used architecture books by Patterson and Hennessy.As one of the original Reduced Instruction Set Computing architectures,MIPS is clean and exceptionally easy to understand and build.MIPS remains an important architecture and has been infused with new energy after Imagination Technologies acquired it in 2013.Over the past two decades,the ARM architecture has exploded in popularity because of its efficiency and rich ecosystem.More than 50 bil-lion ARM processors have been shipped,and more than 75%of humans on the planet use products with ARM processors.At the time of this writ-ing,nearly every cell phone and tablet sold contains one or more ARM processors.Forecasts predict tens of billions more ARM processors soon controlling the Internet of Things.Many companies are building high-per-formance ARM systems to challenge Intel in the server market.Because of the commercial importance and student interest,we have developed this ARM edition of this book.Pedagogically,the learning objectives of the MIPS and ARM editions are identical.The ARM architecture has a number of features including addressing modes and conditional execution that contribute to its effi-ciency but add a small amount of complexity.The microarchitectures also are very similar,with conditional execution and the program counter being the largest changes.The chapter on I/O provides numerous exam-ples using the Raspberry Pi,a very popular ARM-based embedded Linux single board computer.We expect to offer both MIPS and ARM editions as long as the mar-ket demands.FEATURESSide-by-Side Coverage of SystemVerilog and VHDLHardware description languages(HDLs)are at the center of modern digi-tal design practices.Unfortunately,designers are evenly split between the two dominant languages,SystemVerilog and VHDL.This book intro-duces HDLs in Chapter 4 as soon as combinational and sequential logic design has been covered.HDLs are then used in Chapters 5 and 7 to design larger building blocks and entire processors.Nevertheless,Chapter 4 can be skipped and the later chapters are still accessible for courses that choose not to cover HDLs.This book is unique in its side-by-side presentation of SystemVerilog and VHDL,enabling the reader to learn the two languages.Chapter 4 describes principles that apply to both HDLs,and then provides language-specific syntax and examples in adjacent columns.This side-by-side treatment makes it easy for an instructor to choose either HDL,and for the reader to transition from one to the other,either in a class or in professional practice.ARM Architecture and MicroarchitectureChapters 6 and 7 offer the first in-depth coverage of the ARM architec-ture and microarchitecture.ARM is an ideal architecture because it is a real architecture shipped in millions of products yearly,yet it is stream-lined and easy to learn.Moreover,because of its popularity in the com-mercial and hobbyist worlds,simulation and development tools exist for the ARM architecture.All material relating to ARM.technology has been reproduced with permission from ARM Limited.Real-World PerspectivesIn addition to the real-world perspective in discussing the ARM architec-ture,Chapter 6 illustrates the architecture of Intel x86 processors to offer another per
莎拉L.哈里斯（Sarah L.Harris）內華達大學電子與計算機工程系副教授，擁有斯坦福大學電子工程博士學位。她曾在惠普、圣地亞哥超算中心、英偉達公司和微軟亞洲研究院工作，擅長計算機體系結構設計和系統設計。戴維·莫尼·哈里斯（David Money Harris）哈維瑪德學院工程系教授，擁有斯坦福大學電子工程博士學位。他曾在英特爾公司從事Itanium和Pentium II處理器的邏輯和電路設計，并曾擔任Sun Microsystems、惠普、Evans&Sutherland等設計公司的顧問，獲得了12項專利。
"Contents
Preface . vi
Features . vii
Online Supplements viii
How to Use the Software Tools in a Course ix
Labs ix
Bugs x
Acknowledgments xi
Chapter 1 From Zero to One 3
1.1 TheGamePlan 3
1.2 The Art of Managing Complexity . 4
1.2.1 Abstraction 4
1.2.2 Discipline 5
1.2.3 The Three-Y’s 6
1.3 The Digital Abstraction 7
1.4 Number Systems. 9
1.4.1 Decimal Numbers 9
1.4.2 Binary Numbers 9
1.4.3 Hexadecimal Numbers . 11
1.4.4 Bytes, Nibbles, and All That Jazz . 13
1.4.5 Binary Addition . 14
1.4.6 Signed Binary Numbers 15
1.5 Logic Gates 19
1.5.1 NOT Gate 20
1.5.2 Buffer 20
1.5.3 AND Gate 20
1.5.4 OR Gate . 21
1.5.5 Other Two-Input Gates 21
1.5.6 Multiple-Input Gates . 21
1.6 Beneath the Digital Abstraction 22
1.6.1 Supply Voltage 22
1.6.2 Logic Levels 22
1.6.3 Noise Margins 23
1.6.4 DC Transfer Characteristics 24
1.6.5 The Static Discipline . 24
1.7 CMOSTransistors 26
1.7.1 Semiconductors 27
1.7.2 Diodes 27
1.7.3 Capacitors 28
1.7.4 nMOS and pMOS Transistors 28
1.7.5 CMOS NOT Gate . 31
1.7.6 Other CMOS Logic Gates . 31
1.7.7 Transmission Gates 33
1.7.8 Pseudo-nMOS Logic . 33
1.8 Power Consumption 34
1.9 Summary and a Look Ahead 35
Exercises 37
Interview Questions . 52
Chapter 2 Combinational Logic Design 55
2.1 Introduction 55
2.2 BooleanEquations 58
2.2.1 Terminology 58
2.2.2 Sum-of-Products Form . 58
2.2.3 Product-of-Sums Form . 60
2.3 BooleanAlgebra 60
2.3.1 Axioms . 61
2.3.2 Theorems of One Variable . 61
2.3.3 Theorems of Several Variables 62
2.3.4 The Truth Behind It All 64
2.3.5 Simplifying Equations 65
2.4 From Logic to Gates 66
2.5 Multilevel Combinational Logic 69
2.5.1 Hardware Reduction . 70
2.5.2 Bubble Pushing 71
2.6 X’s and Z’s, Oh My 73
2.6.1 Illegal Value: X . 73
2.6.2 Floating Value: Z 74
2.7 Karnaugh Maps 75
2.7.1 Circular Thinking . 76
2.7.2 Logic Minimization with K-Maps . 77
2.7.3 Don't Cares . 81
2.7.4 The Big Picture 82
2.8 Combinational Building Blocks 83
2.8.1 Multiplexers . 83
2.8.2 Decoders . 86
2.9 Timing. 88
2.9.1 Propagation and Contamination Delay 88
2.9.2 Glitches . 92
2.10 Summary 95
Exercises 97
Interview Questions 106
Chapter 3 Sequential Logic Design 109
3.1 Introduction. 109
3.2 Latches and Flip-Flops . 109
3.2.1 SR Latch . 111
3.2.2 D Latch 113
3.2.3 D FIip-Flop . 114
3.2.4 Register . 114
3.2.5 Enabled Flip-Flop . 115
3.2.6 Resettable Flip-Flop 116
3.2.7 Transistor-Level Latch and Flip-Flop Designs 116
3.2.8 Putting It All Together . 118
3.3 Synchronous Logic Design 119
3.3.1 Some Problematic Circuits 119
3.3.2 Synchronous Sequential Circuits 120
3.3.3 Synchronous and Asynchronous Circuits . 122
3.4 Finite State Machines 123
3.4.1 FSM Design Example 123
3.4.2 State Encodings . 129
3.4.3 Moore and Mealy Machines 132
3.4.4 Factoring State Machines . 134
3.4.5 Deriving an FSM from a Schematic . 137
3.4.6 FSM Review 140
3.5 Timing of Sequential Logic . 141
3.5.1 The Dynamic Discipline 142
3.5.2 System Timing 142
3.5.3 Clock Skew . 148
3.5.4 Metastability 151
3.5.5 Synchronizers . 152
3.5.6 Derivation of Resolution Time 154
3.6 Parallelism 157
3.7 Summary . 161
Exercises 162
Interview Questions 171
Chapter 4 Hardware Description Languages 173
4.1 Introduction. 173
4.1.1 Modules 173
4.1.2 Language Origins . 174
4.1.3 Simulation and Synthesis . 175
4.2 Combinational Logic. 177
4.2.1 Bitwise Operators . 177
4.2.2 Comments and White Space 180
4.2.3 Reduction Operators . 180
4.2.4 Conditional Assignment 181
4.2.5 Internal Variables . 182
4.2.6 Precedence 184
4.2.7 Numbers 185
4.2.8 Z’s and X’s . 186
4.2.9 Bit Swizzling 188
4.2.10 Delays 188
4.3 Structural Modeling 190
4.4 Sequential Logic . 193
4.4.1 Registers 193
4.4.2 Resettable Registers 194
4.4.3 Enabled Registers 196
4.4.4 Multiple Registers . 197
4.4.5 Latches . 198
4.5 MoreCombinationalLogic. 198
4.5.1 Case Statements . 201
4.5.2 If Statements 202
4.5.3 Truth Tables with Don’t Cares . 205
4.5.4 Blocking and Nonblocking Assi"
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